Some systems require a reliable and low latency bidirectional data link between chips. For example, such links are useful in systems of multiple processors in multiple chips where a processor in one chip accesses a memory interface of the other chip through a dedicated link between the processor chips. Such systems occur in, for example, a mobile phone in which a modem processor chip and an applications processor chip connect using the Mobile Industry Processor Interface Low Latency Interface (MIPI LLI) protocol to share a double data rate dynamic (DDR) random access memory (RAM). The chips may be integrated circuits in different packages or integrated circuits inside the same package. They may also be implemented in multiple integrated circuits.
In such systems a multi layer protocol is used. A data link layer assumes the error free transmission of data from sender to receiver. The data link layer sends discrete amounts of data referred to as frames. A physical (PHY) layer is below the data link layer. The PHY layer sends the frame as well as control information. The physical link is assumed to be lossy, and the PHY layer is responsible for providing error free transmission of frames. Such systems implement an error detection algorithm in the receiver, and indicate errors to the sender. Upon the receiving an indication of an error, the sender retransmits frames from a buffer called a retry buffer.
The protocol is implemented by a controller within each chip, such as controller 100 shown in FIG. 1. Controller 100 includes retry buffer 10 coupled to transmitter 104. Transmitter 104 is configured to transmit frames across link 106 and controller 100 stores the sent frames in retry buffer 102. Signals 110, 108 referred to as ACK and NACK, respectively, are received from a receiving controller (not shown) on the other side of link 106 to indicate, respectively, complete error-free reception and a detected transmission error.
The receiving chip performs error detection on the frame that is received. The method of error detection could be a parity check on symbols, running disparity errors, badly formed frame detection, frame cyclic redundancy check (CRC) errors and sequence errors, or other error detection methods. The receiving chip gives an indication of ACK 110 for every frame or group of frames received free of errors. The receiving chip gives an indication of NACK 108 for every frame or group of frames received with an error.
When controller 100 gets an ACK 110 indication it discards the corresponding frame from retry buffer 102. When controller 100 gets a NACK 108 indication it takes from retry 102 buffer at least the frame that was received in error and retransmits it from transmitter 100 on link 106. Peripheral Component Interconnect Express (PCI Express) is such a example protocol, using both ACKs and NACKs in-band, in addition to a timeout on the reception of ACKs as an additional source of error detection.
One problem with such state of the art protocols is that either the ACK indication takes extra pins between chips or it is in-band and consumes extra bandwidth. What is needed is a smarter retry buffer management protocol and controller that does not require ACK signaling.